1. Field of the Invention
The invention relates to an electrical circuit timing and verification system, and particularly to a computer-based system that automates and facilitates the entry, modification, analysis and generation of test benches in multiple HDL digital hardware designs via a unique wavetable spreadsheet interface which simultaneously displays data as both waveforms and numerical cell values.
2. Description of Related Art
Hardware Description Languages (HDLs) are language specifications for precisely describing the behavior and programming the function of electrical circuits. Test benches are HDL descriptions specialized in describing and verifying the behavior of electrical circuits.
Events and data in electrical circuits are routinely described by signals (one bit wide), and vectors (two or more bits wide). The manner in which signals and vectors change as time flows are described by displaying signal snapshots sequentially. The resulting object is called a waveform.
If signal waveforms are not properly synchronized, the electrical circuit may not behave as intended, and consequently generate unwanted operational errors.
When a circuit is built, an engineer will use timing verification techniques to identify such errors such that they can be eliminated.
One popular timing verification technique is the creation of timing waveforms to describe the logical relationships, values, and timing constraints among the signals in a given electrical circuit.
A technique for testing the behavior of electrical circuits under arbitrary and specific input data streams are also needed to detect data sensitive errors. Spreadsheet-based tables of signal data streams stacked on top of each other are commonly used to spot data-sensitive errors. However, because table-based descriptions of data lacks visual content, it is inherently ill suited to convey the logical relationship among the same data. These tables are usually generated manually via programming scripts of varying complexity.
HDL simulators are typically used to test and visualize all the various logical and physical conditions that will influence the behavior and proper function of an electrical circuit.
A problem with simulators is that they cannot be used until the behavioral description of the design has been properly and manually encoded as a script or as an HDL test bench description. This in itself is an error-prone and tedious process.
Likewise, HDL test bench descriptions of test pattern data are, by themselves, static, thereby requiring considerable effort to modify in response to changes in the underlying electrical circuit specification.
Another problem with traditional simulators is that, once a problem is encountered, the test pattern must be modified manually in order to keep it up to date.
Thus, it is highly desirable to create a “seamless” two-way link between the HDL description of the electrical circuit, and the test pattern used to verify it.
Furthermore, in a truly seamless test environment, changes in the specification of the circuit interface to the outside world would have to be automatically reflected in the test pattern itself. Were this not the case, any HDL test bench description generated from the test pattern would no longer correctly reflect the user's intent.
Because HDL test benches are the standard format used by engineers to test designs with HDL simulators, there is a need for automating their entry, modification, and generation, resulting in HDL descriptions that are both quantitatively and qualitatively correct.
The present invention also addresses the problem which arises when an HDL design (VHDL or VERILOG®, or other HDLs) is synthesized to a HDL netlist and the resulting netlist may not be compatible with test benches created for the pre-synthesis HDL source. The most common reasons for this are:
Unused inputs are optimized out during synthesis, and therefore not present in the port list;
A signal is defined as bi-directional (inout, buffer) in the HDL source, but is used only as an output. Synthesis correctly recognizes the signal is uni-directional and changes the port mode from bi-directional to uni-directional;
Complex data types are remapped to synthesized types. An example is in VHDL the INTEGER data type is remapped to std_logic_vector; or
Parameters (VERILOG®) and Generics (VHDL) are used pre-synthesis to set up the design. Once synthesized, these are dropped from the port definition. Pre-synthesis test benches must instantiate the design using the parameter for it to function as intended. Post-synthesis designs have been flattened, and no parameters remain in the ports; or
Partially used vectors (those with some unused bits) are changed in width; or
The order of signals in the port is changed, thereby causing test benches which rely on port order for instantiation to be incompatible.
The net result is that the test engineer needs to modify all test benches to accommodate to the changes. The designer needs to update all port definitions, component instantiations, signal assignments, and output assertions. Each time changes are made to the pre-synthesis design (then synthesized) the test benches need to be re-updated to maintain consistency.
For example, pre-synthesis VHDL definition for a counter might look like the following:
entity counter isPort (CLK : in std_logic;RESET : in std_logic;CE : in std_logic;COUNT : inout integer range 0 to 7 := 0);end counter;
After synthesis, the VHDL netlist ports look like this:
entity COUNTER isport (CE : in STD_LOGIC := ′X′;CLK : in STD_LOGIC := ′X′;RESET : in STD_LOGIC := ′X′;COUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ));end COUNTER;
Notice the last item (COUNT) in the pre-synthesis definition is:                COUNT: inout integer range 0 to 7:=0        
In this case the counter is of mode “inout” and is of type “integer”.
After synthesis it becomes:                COUNT: out STD_LOGIC_VECTOR (2 downto 0)        
Notice the mode is now “out” and the type is “std_logic_vector”.
The changes made during synthesis render the pre-synthesis (behavioral) test benches unusable without modification. Normally the test benches must be updated by hand. All ports must be updated to match the synthesized netlist. Generics (and parameters) must be eliminated. Unused signals must be stripped from the port and the test bench. The test bench code must then be revised, changing all input assignments, check procedures, file IO and other portions of the test bench which are affected by/signal definition changes and port changes.
During simulation and synthesis of behavioral designs, attributes are passed to the unit under test via generics or parameters. These attributes can be changed in the behavioral description. The last value assumed by the generics must be used during the remap process to ensure continuity between behavioral and post-synthesis testing.
One solution to this problem is to restrict the HDL constructs used in a design. For example, allowing only std_logic_vectors in place of integers might eliminate data type remapping. Port mode changes can be resolved (manually) by back annotating the synthesized port modes into the original behavioral HDL source. While these solutions reduce the occurrences of port map problems, they do not eliminate them.
The present invention addresses this problem by including an Automatic Post Synthesis Test Bench Remap feature that automatically re-maps signals based upon their name, mode and data type.